This is a patent application based on a Japanese patent application No. 2001-168936 which was filed on Jun. 5, 2001 and which is incorporated herein by reference.
1. Field of the Invention
The present invention relates to a Group III nitride compound semiconductor element which is produced through steps including a step of growing semiconductor crystals and a separation step for producing chips of the produced semiconductor wafer (semiconductor elements), and to a method for producing the Group III nitride compound semiconductor.
2. Background Art
As shown in FIG. 5 and as is widely known, when a Group III nitride compound semiconductor such as gallium nitride (GaN) grown on the Si(111) planexe2x80x94serving as a crystal growth plane (crystal growth region)xe2x80x94of a silicon substrate is cooled to ambient temperature, a number of dislocations and cracks are generated in the grown semiconductor layer.
When a number of dislocations and cracks are generated in the grown layer (nitride semiconductor layer), a number of lattice defects, dislocations, deformation, cracks, etc., are generated in a device fabricated from the semiconductor layer, thereby deteriorating device characteristics.
In the case in which hexagonal GaN crystals are grown on a silicon substrate having a so-called diamond structure, the Si(111) planexe2x80x94closest packing planexe2x80x94is typically employed as a crystal growth plane. In the process in which a customary semiconductor element having a rectangular plane shape is formed through crystal growth on the Si(111) plane and a plurality of individual semiconductor elements (chips) are separated from the semiconductor wafer, at least two sidewalls of the semiconductor element are composed of two cleavable cutting planes. Thus, a scribing step becomes cumbersome or difficult, thereby prolonging a production time or tending to provide defective products having deteriorated device characteristics caused by cracks, etc. As a result, productivity cannot be enhanced.
In addition, when a customary semiconductor element of a rectangular shape is formed on the Si(111) plane, an allowance region for scribing in the aforementioned scribing step occupies a considerably large area of the semiconductor wafer, thereby failing to enhance semiconductor wafer utilization efficiency (yield).
The present invention has been accomplished in order to overcome the aforementioned drawbacks. Thus, an object of the present invention is to produce, at high efficiency, semiconductor elements which are formed of a high-quality crystalline semiconductor having low dislocation density and no cracks and which have excellent characteristics.
According to first means to overcome the above-described drawbacks, the present invention provides a method for producing a semiconductor element comprising growing a crystalline semiconductor A formed of a Group III nitride compound semiconductor on a crystal growth region provided on the Si(111) plane of a silicon substrate, the crystal growth region being limited in terms of its area by means of masking or a similar technique, wherein the entirety or a portion of the periphery of the crystal growth region generally coincides with an edge defined by the Si(111) plane and another crystal plane that is cleavable.
The semiconductor layer composed of the aforementioned crystalline semiconductor A may have a single-layer structure or a multi-layer structure.
As used herein, the term xe2x80x9cGroup III nitride compound semiconductorxe2x80x9d generally refers to a 2-component, 3-component, or 4-component semiconductor having arbitrary compound crystal proportions and represented by AlxGayIn(1xe2x88x92xxe2x88x92y)N (0xe2x89xa6xxe2x89xa61; 0xe2x89xa6yxe2x89xa61; 0xe2x89xa6x+yxe2x89xa61). The xe2x80x9cGroup III nitride compound semiconductorxe2x80x9d of the present invention also encompasses such species containing a p-type or n-type dopant.
In the present specification, the xe2x80x9cGroup III nitride compound semiconductorxe2x80x9d also encompasses semiconductors in which the aforementioned Group III elements (Al, Ga, In) are partially substituted by boron (B), thallium (Tl), etc. or in which nitrogen (N) atoms are partially substituted by phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), etc.
Examples of the p-type dopant which can be added include magnesium (Mg) and calcium (Ca).
Examples of the n-type dopant which can be added include silicon (Si), sulfur (S), selenium (Se), tellurium (Te), and germanium (Ge).
These dopants may be used in combination of two or more species, and a p-type dopant and an n-type dopant may be added simultaneously.
As described above, when the entire periphery of the crystal growth region is composed of edges each defined by two planes; i.e., the Si(111) plane and another crystal plane that is cleavable (or in other words, crystal plane of cleavage fracture), the entire sidewall of the silicon substrate belonging to each semiconductor element is exclusively composed of a cleavable silicon crystal plane. Thus, the scribing step is remarkably simplified, thereby shortening the production time, and defective products having deteriorated device characteristics caused by cracks, etc. can be decreased, leading to remarkable enhancement in productivity. In addition, cutting allowance required for scribing can be reduced considerably, leading to remarkable improvement of yield.
When an Si(1-10) crystal plane is employed as a cleavable crystal plane, the Si(1-10) crystal plane and a GaN(11-20) plane coincide, thereby reducing the amount of material rise at a peripheral portion of the crystal growth region. Thus, the crystal growth plane of the wafer can be further flattened, thereby increasing the yield of flat portions.
In contrast to the case in which a customary rectangular (generally rectangle) growth region is provided, according to the present invention, the growth rate is substantially uniform over the entire peripheral portion of the crystal growth region, since all edges surrounding the crystal growth region are composed of equivalent planes; i.e., [1-10]. Thus, the thickness of the growth layer at the peripheral portion of the crystal growth region becomes substantially uniform, and therefore, the width of the emission wavelength (half-value (emission intensity) width of the emission wavelength) decreases, to thereby enable production of a light-emitting element having an emission wavelength with small variation and an intense emission peak.
In the aforementioned first aspect, the crystalline semiconductor A is preferably formed of a Group III nitride compound semiconductor represented by AlxGayIn(1xe2x88x92xxe2x88x92y)N (0xe2x89xa6xxe2x89xa61; 0xe2x89xa6yxe2x89xa61; 0xe2x89xa6x+yxe2x89xa61).
In the aforementioned first aspect, the crystal plane that is cleavable is preferably selected from a (-101) plane, a (1-10) plane, and a (01-1) plane of the aforementioned silicon substrate.
For example, as shown in FIG. 1, these three planes are selected in order to provide equilateral triangular crystal growth regions. The combination of these cleavable crystal planes is arbitrary. For example, as shown in FIG. 2, when equilateral triangular crystal growth regions are provided, those arranged in opposite orientations (i.e., those whose orientations differ by 180xc2x0) can be provided.
By employing such cleavable crystal planes serving as sidewalls of a semiconductor element, a scribing step can be simplified.
However, the sides of the periphery of one light-emitting element are not necessarily provided simultaneously from all the three planes. When at least one side of the periphery of the light-emitting element is composed of the aforementioned edge, the aforementioned advantages are attained to at least some extent. For example, a light-emitting element may have a right triangle plane shape having a top angle of approximately 60xc2x0, and two sides forming the angle may be composed of the aforementioned edge. Through employment of such a plane shape, the aforementioned advantages are also attained to an extent similar to or greater than that attained above.
In the first aspect, the aforementioned crystal growth region preferably has a shape or an approximate shape of an equilateral triangle, parallelogram, isosceles trapezoid, or equiangular hexagon. The shape or approximate shape may be a pentagon having only one acute-angled (60xc2x0) apex, and the aforementioned equiangular hexagon may be equilateral or scalene.
Particularly, when equilateral triangle arrangement or parallelogram arrangement of crystal growth regions is employed, planes of semiconductor elements can be arranged in a semiconductor wafer at high packing density without loss. In addition, each side of these semiconductor elements can be readily arranged in a line on the wafer, thereby remarkably facilitating scribing. Thus, quality and productivity of semiconductor elements can be further enhanced.
In the first aspect, preferably, a single element of the semiconductor element is formed on a single region of the crystal growth region. In other words, the dimensions and shape of the crystal growth region are caused to generally coincide with those of the semiconductor element.
As described above, limiting the area of one crystal growth region to a small area limits or suppresses cracks generated due to a stress attributed to differences in lattice constant and thermal expansion coefficient and exerted between a silicon substrate and a semiconductor layer (crystalline semiconductor A). Thus, semiconductor elements having excellent crystallinity can be readily produced.
Despite employment of a thick silicon substrate, in which relaxation of stress generated in a semiconductor element is difficult, application of a stress to a semiconductor layer (crystalline semiconductor A) is mitigated by limiting the area of one crystal growth region to a very small area. Thus, a thin-film silicon substrate, which readily relaxes the stress applied to a semiconductor layer and tends to break, does not have to be employed as a crystal growth substrate (Si substrate), thereby attaining easy handling of silicon substrates and leading to enhancement of productivity and quality.
In second aspect, there is provided a Group III nitride compound semiconductor element produced through employment of the structure based on the aforementioned first aspect.
The second aspect is drawn to the structure or configuration of the semiconductor element per se. Specifically, there is provided a Group III nitride compound semiconductor element produced by growing crystalline semiconductor A formed of a Group III nitride compound semiconductor on a crystal growth region provided on the Si(111) plane of a silicon substrate, the crystal growth region being limited in terms of its area by aspect of masking or a similar technique, wherein the entirety or a portion of the periphery of the crystal growth region generally coincides with an edge defined by the Si(111) plane and another crystal plane that is cleavable.
In addition to the above second aspect, at least one of the below-described preferred element structure is employed.
Specifically, the aforementioned crystalline semiconductor A is formed of a Group III nitride compound semiconductor represented by AlxGayIn(1xe2x88x92xxe2x88x92y)N (0xe2x89xa6xxe2x89xa61; 0xe2x89xa6yxe2x89xa61; 0xe2x89xa6x+yxe2x89xa61).
The aforementioned crystal plane that is cleavable is selected from a (-101) plane, a (1-10) plane, and a (01-1) plane of the aforementioned silicon substrate.
The periphery of the aforementioned crystal growth region has a shape or an approximate shape of an equilateral triangle, parallelogram, isosceles trapezoid, or equiangular hexagon.
One semiconductor element is formed on one crystal growth region. In other words, the dimensions and shape of the crystal growth region are caused to generally coincide with those of the semiconductor element.
Through employment of the aforementioned aspect of the present invention, the aforementioned drawbacks can be overcome effectively and rationally.